1. Field
This invention is directed to a method or apparatus for making engineering changes to integrated circuit packages. It is directed more particularly to providing for quick turnaround engineering changes involving more than one level of a multiple-level circuit package, and also to allow for ongoing incremental engineering changes.
High density integrated circuit packaging involves a hierarchy of packaging levels. A typical multi-level hierarchy involves integrated circuit chips (the highest level) mounted on circuit modules, with the modules mounted on printed circuit cards, and the cards mounted on printed circuit boards (the lowest level). A card or a board can be connected to another card or board by a cable. A level can be omitted, for example chips can be mounted directly on cards or boards, and modules can be mounted on boards. When design changes become necessary, an engineering change (EC) will frequently involve more than one packaging level.
When an EC involves more than one packaging level, the turnaround time to complete the EC is gated by the turnaround time of the slowest EC. Chip ECs are relatively quick, with the advent of FIB, or Focussed Ion Beam process, as explained in IBM Technical Disclosure Bulletin Vol. 36 No 7 July 1993 by Bellwood et al. entitled "Verification and Implementation of Post-Manufacturing Chip Design Change" and incorporated herein in its entirety. The FIB process avoids changing masks and rebuilding the chip. It involves blasting a hole in the chip with a laser, cutting connections, or adding connections with ion implantation and closing the hole. As a result, chip ECs can be completed in a few days. Module and card ECs are more complex and take months, while board ECs can take three times as long as modules or cards. Prior to this invention, a board EC involved adding, deleting, or otherwise modifying a wired connection on a board, as well as ECing at least one module or card on that board. The board EC usually entails disconnecting a board wire from the board via. The wire may then be drilled out, backfilled with an insulated connection, and discretely wired on the bottom surface of the board. Thus even if the EC process for the different packages involved is performed in parallel, the total time to EC will still be the time for the slowest package EC, which typically involves the lowest level of packaging.
2. Prior Art
Previous inventions have attempted to provide a way of making engineering changes to circuit and module designs. Programmable gate arrays provide a layout of predefined gates in a chip which are customized, or "burned in" by applying external signals. Memory chips use redundant memory blocks and spare data lines to support repairs of defects. Other inventions make changes in the wiring pattern of a printed circuit board by attaching an auxiliary board. Yet other inventions add new chips or components by attaching a card or board to a module. Inventions addressing two-level package hierarchies with chips mounted on a module make changes with EC lines buried in the module and customizable surface connections to the chips, for example in U.S. Pat. No. 4,489,364 issued Dec. 18, 1984 to Chance, et al and incorporated by reference herein in its entirety.
Spare I/O was the focus of an IBM Technical Disclosure Bulletin Vol. 34, No. 10A, March 1992, by Sanders et al entitled "Spare I/O Preparation for Use at Release Interface Tape B." Sanders' method applied to a specific module and called for setting up spare I/O as common I/O configured as a control or data net. The method did not add surplus connections, nor did it apply to connections other than data lines; it utilized unused drivers and receivers on two chips rather directly using surplus I/O at any level of packaging hierarchy. This method addressed the goal of reducing product design cycles but like other inventions failed to provide quick turnaround post-manufacture engineering changes across multiple levels of integrated circuit packaging and the ability to support ongoing incremental engineering changes.